Running in Lattice mode

                               Synplify Pro (R) 

                 Version V-2023.09L-2 for win64 - Sep 17, 2024 

                    Copyright (c) 1988 - 2024 Synopsys, Inc.
   This software and the associated documentation are proprietary to Synopsys,
 Inc. This software may only be used in accordance with the terms and conditions
 of a written license agreement with Synopsys, Inc. All other use, reproduction,
   or distribution of this software is strictly prohibited.  Licensed Products
     communicate with Synopsys servers for the purpose of providing software
    updates, detecting software piracy and verifying that customers are using
    Licensed Products in conformity with the applicable License Key for such
  Licensed Products. Synopsys will use information gathered in connection with
    this process to deliver software updates and pursue software pirates and
                                   infringers.

 Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
            Inclusivity and Diversity" (Refer to article 000036315 at
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Starting:    C:\ToolSoftware\Diamond\3.14\synpbase\bin64\mbin\synbatch.exe
Install:     C:\ToolSoftware\Diamond\3.14\synpbase
Hostname:    DESKTOP-LK1D0PP
Date:        Sun Nov 17 20:33:49 2024
Version:     V-2023.09L-2

Arguments:   -product synplify_base -batch CL202_MXO2_2000HC_synplify.tcl
ProductType: synplify_pro





log file: "D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr"
Running: hdl_info_gen in foreground

Generating HDL info...
Copied D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr to D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srf

hdl_info_gen completed
# Sun Nov 17 20:33:50 2024

Return Code: 0
Run Time:00h:00m:00s
log file: "D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr"
Running: MXO2_2000HC in foreground

Running proj_1|MXO2_2000HC

Running Flow: compile (Compile) on proj_1|MXO2_2000HC
# Sun Nov 17 20:33:50 2024

Running Flow: compile_flow (Compile Process) on proj_1|MXO2_2000HC
# Sun Nov 17 20:33:50 2024

Running: compiler (Compile Input) on proj_1|MXO2_2000HC
# Sun Nov 17 20:33:50 2024
Copied D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_comp.srs to D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srs

compiler completed
# Sun Nov 17 20:33:53 2024

Return Code: 0
Run Time:00h:00m:02s

Running: multi_srs_gen (Multi-srs Generator) on proj_1|MXO2_2000HC
# Sun Nov 17 20:33:53 2024

multi_srs_gen completed
# Sun Nov 17 20:33:53 2024

Return Code: 0
Run Time:00h:00m:00s
Copied D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_mult.srs to D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srs
Copied D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr to D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srf
Complete: Compile Process on proj_1|MXO2_2000HC

Running: premap (Premap) on proj_1|MXO2_2000HC
# Sun Nov 17 20:33:53 2024

premap completed with warnings
# Sun Nov 17 20:33:55 2024

Return Code: 1
Run Time:00h:00m:02s
Complete: Compile on proj_1|MXO2_2000HC

Running Flow: map (Map) on proj_1|MXO2_2000HC
# Sun Nov 17 20:33:55 2024
License granted for 4 parallel jobs

Running: fpga_mapper (Map & Optimize) on proj_1|MXO2_2000HC
# Sun Nov 17 20:33:55 2024
Copied D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_m.srm to D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srm

fpga_mapper completed with warnings
# Sun Nov 17 20:33:59 2024

Return Code: 1
Run Time:00h:00m:04s
Complete: Map on proj_1|MXO2_2000HC
Copied D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr to D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srf
Complete: Logic Synthesis on proj_1|MXO2_2000HC
TCL script complete: "CL202_MXO2_2000HC_synplify.tcl"
exit status=0
exit status=0
Save changes for project:
D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\proj_1.prj
batch mode default:no
